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Task #3034

open

Task #2985: Detailed Design

Task #2989: Embedded SW-Development

DI Module

Task #3034: DI Module

Added by Thomas Joseph 4 months ago. Updated about 1 month ago.

Status:
Resolved
Priority:
Normal
Assignee:
Sumanth D
Target version:
-
Start date:
20/03/2026
Due date:
07/04/2026 (27 days late)
% Done:

100%

Estimated time:
Spent time:
17:30 h

Description

  1. CLT01-38S, SPI based.
  2. Refer PLCIO Programming model => https://elpisit-my.sharepoint.com/:x:/g/personal/satish_sl_elpisitsolutions_com/IQBrgmGfi3IqRIQq1gZEsIDkASmEjqWfOCF4OvW6dEpouCI?e=lhdHPU
  3. S/W references

a. TV2.1, TV3 DI Module (L21, Baremetal)
b. eVidya (SAMDx, Linux)

Files

clipboard-202602241934-2ro59.png (221 KB) clipboard-202602241934-2ro59.png Sumanth D, 24/02/2026 02:04 PM
clipboard-202602241934-2ro59.png

Updated by Thomas Joseph 4 months ago Actions
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 #1

  • Description updated (diff)

Updated by Thomas Joseph 4 months ago Actions
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 #2

  • Due date set to 19/01/2026
  • Start date set to 08/01/2026

Updated by Thomas Joseph 4 months ago Actions
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 #3

  • Due date changed from 19/01/2026 to 22/01/2026
  • Start date changed from 08/01/2026 to 20/01/2026

Updated by Thomas Joseph 4 months ago Actions
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 #4

  • Start date changed from 20/01/2026 to 08/01/2026

Updated by Thomas Joseph 3 months ago Actions
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 #5

  • Due date changed from 22/01/2026 to 26/01/2026
  • Assignee set to DEVI PRIYAA

Planned to start porting on 22/01/2026

Updated by DEVI PRIYAA 3 months ago Actions
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 #6

  • Status changed from New to In Progress
  • % Done changed from 0 to 30

Code integrated for DI module.

Updated by Thomas Joseph 3 months ago Actions
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 #7

Discussed with @DEVI PRIYAA :

Currently working on http://5.161.106.25:3000/issues/3243
Will start on 12th, due date extended to 12/02/2026

Updated by Sumanth D 2 months ago Actions
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 #8

  • Assignee changed from DEVI PRIYAA to Sumanth D
  • % Done changed from 30 to 40

For DI SPI clock and Chip set were generating but MOSI and MISO were not coming. It is observed that only one clock cycle is generating(8 pulses) but we need to write 16 bit data.

Updated by Sumanth D 2 months ago Actions
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 #9

  • Assignee changed from Sumanth D to Yoganand D

Updated by Sumanth D 2 months ago Actions
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 #10

clipboard-202602241934-2ro59.png

DI is tested with Different inputs AAAA, 5555,00FF,FF00,F0F0. In these 00FF,FF00,F0F0 these inputs were reflecting on the terminal and the respective waveforms were generated. And for toggling inputs like AAAA, 5555 we were not getting the output in the terminal.

https://elpisit-my.sharepoint.com/:x:/g/personal/satish_sl_elpisitsolutions_com/IQCLSJ5-TJFpQrp3hDAHWTrvAU3Fl2PXWkHaS3Tx6P4ysZM?e=fmKWuU-- this the test result link

Thomas sir suggested to test by changing the SPI CLK frequency to 100kHz or less to correct this issue

!{width: 660px}.clipboard-202602241934-2ro59.png!

Updated by Sumanth D 2 months ago Actions
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 #11

  • % Done changed from 50 to 70

Updated by Sumanth D 2 months ago Actions
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 #12

https://elpisit-my.sharepoint.com/:x:/g/personal/satish_sl_elpisitsolutions_com/IQDwGhtv9DV1R7UiFtU0joQ3AQeLCCimNnREdvTmcrdc-vI?e=KYuUx3

DI testing is completed and results were added in the test document and the link is attached. The input sequences were matching with the terminal print and scope wave forms. And the same were added in the test result document

Updated by Sumanth D 2 months ago Actions
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 #13

  • % Done changed from 70 to 90

Updated by Sumanth D 2 months ago Actions
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 #14

  • Status changed from In Progress to Resolved

Updated by Sumanth D about 2 months ago Actions
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 #15

  • % Done changed from 90 to 100
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